1.. _ctags_lang-verilog(7): 2 3====================================================================== 4ctags-lang-verilog 5====================================================================== 6 7The man page about SystemVerilog/Verilog parser for Universal Ctags 8 9 10:Version: 5.9.0 11:Manual group: Universal Ctags 12:Manual section: 7 13 14SYNOPSIS 15-------- 16| **ctags** ... [--kinds-systemverilog=+Q] [--fields-SystemVerilog=+{parameter}] ... 17| **ctags** ... [--fields-Verilog=+{parameter}] ... 18 19 +---------------+---------------+-------------------+ 20 | Language | Language ID | File Mapping | 21 +===============+===============+===================+ 22 | SystemVerilog | SystemVerilog | .sv, .svh, svi | 23 +---------------+---------------+-------------------+ 24 | Verilog | Verilog | .v | 25 +---------------+---------------+-------------------+ 26 27DESCRIPTION 28----------- 29This man page describes about the SystemVerilog/Verilog parser for Universal Ctags. 30SystemVerilog parser supports IEEE Std 1800-2017 keywords. 31Verilog parser supports IEEE Std 1364-2005 keywords. 32 33Supported Kinds 34~~~~~~~~~~~~~~~ 35 36.. code-block:: console 37 38 $ ctags --list-kinds-full=SystemVerilog 39 #LETTER NAME ENABLED REFONLY NROLES MASTER DESCRIPTION 40 A assert yes no 0 NONE assertions (assert, assume, cover, restrict) 41 C class yes no 0 NONE classes 42 E enum yes no 0 NONE enumerators 43 H checker yes no 0 NONE checkers 44 I interface yes no 0 NONE interfaces 45 K package yes no 0 NONE packages 46 L clocking yes no 0 NONE clocking 47 M modport yes no 0 NONE modports 48 N nettype yes no 0 NONE nettype declarations 49 O constraint yes no 0 NONE constraints 50 P program yes no 0 NONE programs 51 Q prototype no no 0 NONE prototypes (extern, pure) 52 R property yes no 0 NONE properties 53 S struct yes no 0 NONE structs and unions 54 T typedef yes no 0 NONE type declarations 55 V covergroup yes no 0 NONE covergroups 56 b block yes no 0 NONE blocks (begin, fork) 57 c constant yes no 0 NONE constants (define, parameter, specparam, enum values) 58 e event yes no 0 NONE events 59 f function yes no 0 NONE functions 60 i instance yes no 0 NONE instances of module or interface 61 l ifclass yes no 0 NONE interface class 62 m module yes no 0 NONE modules 63 n net yes no 0 NONE net data types 64 p port yes no 0 NONE ports 65 q sequence yes no 0 NONE sequences 66 r register yes no 0 NONE variable data types 67 t task yes no 0 NONE tasks 68 w member yes no 0 NONE struct and union members 69 70Note that ``prototype`` (``Q``) is disabled by default. 71 72.. code-block:: console 73 74 $ ctags --list-kinds-full=Verilog 75 #LETTER NAME ENABLED REFONLY NROLES MASTER DESCRIPTION 76 b block yes no 0 NONE blocks (begin, fork) 77 c constant yes no 0 NONE constants (define, parameter, specparam) 78 e event yes no 0 NONE events 79 f function yes no 0 NONE functions 80 i instance yes no 0 NONE instances of module 81 m module yes no 0 NONE modules 82 n net yes no 0 NONE net data types 83 p port yes no 0 NONE ports 84 r register yes no 0 NONE variable data types 85 t task yes no 0 NONE tasks 86 87Supported Language Specific Fields 88~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 89 90.. code-block:: console 91 92 $ ctags --list-fields=Verilog 93 #LETTER NAME ENABLED LANGUAGE JSTYPE FIXED DESCRIPTION 94 - parameter no Verilog --b no parameter whose value can be overridden. 95 $ ctags --list-fields=SystemVerilog 96 #LETTER NAME ENABLED LANGUAGE JSTYPE FIXED DESCRIPTION 97 - parameter no SystemVerilog --b no parameter whose value can be overridden. 98 99``parameter`` field 100.................... 101 102If the field ``parameter`` is enabled, a field ``parameter:`` is added on a parameter whose 103value can be overridden on an instantiated module, interface, or program. 104This is useful for a editor plugin or extension to enable auto-instantiation of modules with 105parameters which can be overridden. 106 107.. code-block:: console 108 109 $ ctags ... --fields-Verilog=+{parameter} ... 110 $ ctags ... --fields-SystemVerilog=+{parameter} ... 111 112On the following source code fields ``parameter:`` are added on 113parameters ``P*``, not on ones ``L*``. Note that ``L4`` and ``L6`` is declared by 114``parameter`` statement, but fields ``parameter:`` are not added, 115because they cannot be overridden. 116 117"input.sv" 118 119.. code-block:: systemverilog 120 121 // compilation unit scope 122 parameter L1 = "synonym for the localparam"; 123 124 module with_parameter_port_list #( 125 P1, 126 localparam L2 = P1+1, 127 parameter P2) 128 ( /*port list...*/ ); 129 parameter L3 = "synonym for the localparam"; 130 localparam L4 = "localparam"; 131 // ... 132 endmodule 133 134 module with_empty_parameter_port_list #() 135 ( /*port list...*/ ); 136 parameter L5 = "synonym for the localparam"; 137 localparam L6 = "localparam"; 138 // ... 139 endmodule 140 141 module no_parameter_port_list 142 ( /*port list...*/ ); 143 parameter P3 = "parameter"; 144 localparam L7 = "localparam"; 145 // ... 146 endmodule 147 148.. code-block:: console 149 150 $ ctags -uo - --fields-SystemVerilog=+{parameter} input.sv 151 L1 input.sv /^parameter L1 = "synonym for the localparam";$/;" c parameter: 152 with_parameter_port_list input.sv /^module with_parameter_port_list #($/;" m 153 P1 input.sv /^ P1,$/;" c module:with_parameter_port_list parameter: 154 L2 input.sv /^ localparam L2 = P1+1,$/;" c module:with_parameter_port_list 155 P2 input.sv /^ parameter P2)$/;" c module:with_parameter_port_list parameter: 156 L3 input.sv /^ parameter L3 = "synonym for the localparam";$/;" c module:with_parameter_port_list 157 L4 input.sv /^ localparam L4 = "localparam";$/;" c module:with_parameter_port_list 158 with_empty_parameter_port_list input.sv /^module with_empty_parameter_port_list #()$/;" m 159 L5 input.sv /^ parameter L5 = "synonym for the localparam";$/;" c module:with_empty_parameter_port_list 160 L6 input.sv /^ localparam L6 = "localparam";$/;" c module:with_empty_parameter_port_list 161 no_parameter_port_list input.sv /^module no_parameter_port_list$/;" m 162 P3 input.sv /^ parameter P3 = "parameter";$/;" c module:no_parameter_port_list parameter: 163 L7 input.sv /^ localparam L7 = "localparam";$/;" c module:no_parameter_port_list 164 165TIPS 166~~~~ 167 168If you want to map files ``*.v`` to SystemVerilog, add 169``--langmap=SystemVerilog:.v`` option. 170 171KNOWN ISSUES 172--------------------------------------------------------------------- 173 174See https://github.com/universal-ctags/ctags/issues/2674 for more information. 175 176SEE ALSO 177-------- 178 179- :ref:`ctags(1) <ctags(1)>` 180- :ref:`ctags-client-tools(7) <ctags-client-tools(7)>` 181- Language Reference Manuals (LRM) 182 - IEEE Standard for SystemVerilog — Unified Hardware Design, Specification, and 183 Verification Language, IEEE Std 1800-2017, 184 https://ieeexplore.ieee.org/document/8299595 185 - IEEE Standard for Verilog Hardware Description Language, IEEE Std 1364-2005, 186 https://ieeexplore.ieee.org/document/1620780 187