1ENTITY_TOP input.vhd /^entity ENTITY_TOP is$/;" entity roles:def end:13 2GEN input.vhd /^ GEN : integer := 0$/;" generic entity:ENTITY_TOP roles:def 3INP input.vhd /^ INP : in std_logic$/;" port entity:ENTITY_TOP roles:def 4arch input.vhd /^architecture arch of ENTITY_TOP is$/;" architecture entity:ENTITY_TOP roles:def end:54 5ENTITY_TOP input.vhd /^architecture arch of ENTITY_TOP is$/;" entity roles:desigend architecture:arch 6sig input.vhd /^ signal sig : std_logic := '0';$/;" signal architecture:ENTITY_TOP.arch roles:def 7ENTITY_1 input.vhd /^ component ENTITY_1$/;" component architecture:ENTITY_TOP.arch roles:def end:25 8GEN input.vhd /^ GEN : integer := 0$/;" generic component:ENTITY_TOP.arch.ENTITY_1 roles:def 9INP input.vhd /^ INP : in std_logic$/;" port component:ENTITY_TOP.arch.ENTITY_1 roles:def 10ENTITY_2 input.vhd /^ component ENTITY_2$/;" component architecture:ENTITY_TOP.arch roles:def end:34 11GEN input.vhd /^ GEN : integer := 0$/;" generic component:ENTITY_TOP.arch.ENTITY_2 roles:def 12INP input.vhd /^ INP : in std_logic$/;" port component:ENTITY_TOP.arch.ENTITY_2 roles:def 13ENTITY_1 input-0.vhd /^entity ENTITY_1 is$/;" entity roles:def end:13 14GEN input-0.vhd /^ GEN : integer := 0$/;" generic entity:ENTITY_1 roles:def 15INP input-0.vhd /^ INP : in std_logic$/;" port entity:ENTITY_1 roles:def 16arch input-0.vhd /^architecture arch of ENTITY_1 is$/;" architecture entity:ENTITY_1 roles:def end:20 17ENTITY_1 input-0.vhd /^architecture arch of ENTITY_1 is$/;" entity roles:desigend architecture:arch 18sig input-0.vhd /^ signal sig : std_logic := '0';$/;" signal architecture:ENTITY_1.arch roles:def 19ENTITY_2 input-1.vhd /^entity ENTITY_2 is$/;" entity roles:def end:13 20GEN input-1.vhd /^ GEN : integer := 0$/;" generic entity:ENTITY_2 roles:def 21INP input-1.vhd /^ INP : in std_logic$/;" port entity:ENTITY_2 roles:def 22arch input-1.vhd /^architecture arch of ENTITY_2 is$/;" architecture entity:ENTITY_2 roles:def end:20 23ENTITY_2 input-1.vhd /^architecture arch of ENTITY_2 is$/;" entity roles:desigend architecture:arch 24sig input-1.vhd /^ signal sig : std_logic := '0';$/;" signal architecture:ENTITY_2.arch roles:def 25