xref: /Universal-ctags/Units/parser-verilog.r/verilog-memleak.d/input.v (revision 7bd9f6d1496ad92b345e2c6ff46fece22a35df44)

// Include module declaration in a comment
// module wrong;
// endmodule
`define DEFINE

module mod (
    a,
    b,c,
    d , e ,
    f,
    g
);

parameter PARAM = 1;

input a,b, c, d ;
output e;
output f;
inout g;

wire a,b,c,d,e;
reg f;
wire g;
real k;
integer l;

task add;
    input x, y;