xref: /Universal-ctags/Units/parser-verilog.r/verilog-instance.d/input.v (revision 05f570795c1078e4fc11228fba9d40621a4d5b7a)
1// Include module declaration in a comment
2
3module foo # (parameter
4              PAR_A = 1,
5              PAR_B = 2
6              )
7   (/*AUTOARG*/
8   // Inputs
9   a, b
10   );
11   input a, b;
12
13endmodule: foo
14
15module top (/*AUTOARG*/
16   // Inputs
17   a, b
18   );
19   //begin: AUTOOUTPUTS
20   /*AUTOOUTPUT*/
21
22   //begin: AUTOINPUTS
23   /*AUTOINPUT*/
24   // Beginning of automatic inputs (from unused autoinst inputs)
25   input                a;                      // To uut3 of foo.v
26   input                b;                      // To uut3 of foo.v
27   // End of automatics
28
29   //begin: AUTOWIREs
30   /*AUTOWIRE*/
31
32   //begin: AUTOREGINPUTs
33   /*AUTOREGINPUT*/
34
35   //begin: AUTOREGs
36   /*AUTOREGINPUT*/
37
38   //begin: AUTOUNUSEDs
39   wire unused_pin;
40   assign unused_pin = |{
41                         /*AUTOUNUSED*/
42                         1'b0} ;
43
44   //begin: AUTOTIEOFFs
45   /*AUTOTIEOFF*/
46   foo uut1 (
47             // Inputs
48             a,
49             b),
50     uut2 (
51           .a (a),
52           .b (b));
53   foo uut3 (/*AUTOINST*/
54             // Inputs
55             .a                         (a),
56             .b                         (b))  ;
57   foo #(3, 4)
58   uut4 (/*AUTOINST*/
59             // Inputs
60             .a                         (a),
61             .b                         (b));
62   foo #(.PAR_A (5),
63         .PAR_B (6))
64   uut5 (/*AUTOINST*/
65         // Inputs
66         .a                         (a),
67         .b                         (b));
68   foo uut6 [10:0]();
69   foo uut7 [1:0][10:0]();
70   foo uut8 () ;
71
72   /*! Function Description
73    *
74    *  \param <name> <description>
75    *
76    *  \return <return value description>
77    */
78
79   function void func_foo(int a);
80
81   endfunction : func_foo
82
83
84
85
86endmodule: top
87