xref: /Universal-ctags/Units/parser-verilog.r/verilog-2001.d/input.v (revision 7bd9f6d1496ad92b345e2c6ff46fece22a35df44)
1// Include module declaration in a comment
2// module wrong;
3// endmodule
4`define DEFINE
5`define DEF_WITH_EQ = 1'd100
6`define DEF_VALUE   1'd100
7
8module mod#(
9    parameter PARAM1 = 10,
10    parameter PARAM2 = 2.0
11) (
12    input wire a,
13    b,c,
14    d ,
15    output wire e ,
16    output reg f,
17    inout wire g
18);
19
20localparam LOCALPARAM = 2**2;
21
22localparam STATE1 = 4'h0,
23           STATE2 = 4'h1,
24           STATE3 = 4'h2,
25           STATE4 = 4'h5    ,
26           STATE5 = 4'h6    ,
27           STATE6 = 4'h7    ,
28           STATE7 = 4'h8;
29
30real k;
31integer l;
32reg signed [3:0] scounter;
33
34task add (
35    input x, y,
36    output z
37);
38    z = x + y;
39endtask
40
41function integer mult (
42    input x,
43    input y);
44    mult = x * y;
45endfunction
46
47function [1:0] func_with_range (k, l);
48    func_with_range = {k, l};
49endfunction
50
51endmodule // mod
52