xref: /Universal-ctags/Units/parser-verilog.r/systemverilog-procedural.d/expected.tags (revision 54c9ecea228d102caa7ea2b000a35f59a5e2d374)
1procedural	input.sv	/^module procedural;$/;"	m
2index	input.sv	/^  int index, rega, regb, result;$/;"	r	module:procedural
3rega	input.sv	/^  int index, rega, regb, result;$/;"	r	module:procedural
4regb	input.sv	/^  int index, rega, regb, result;$/;"	r	module:procedural
5result	input.sv	/^  int index, rega, regb, result;$/;"	r	module:procedural
6expression	input.sv	/^    logic expression, a, result, flaga, flagb;$/;"	r	module:procedural
7a	input.sv	/^    logic expression, a, result, flaga, flagb;$/;"	r	module:procedural
8result	input.sv	/^    logic expression, a, result, flaga, flagb;$/;"	r	module:procedural
9flaga	input.sv	/^    logic expression, a, result, flaga, flagb;$/;"	r	module:procedural
10flagb	input.sv	/^    logic expression, a, result, flaga, flagb;$/;"	r	module:procedural
11b	input.sv	/^    logic [2:1] b;$/;"	r	module:procedural
12select	input.sv	/^    logic [1:2] select;$/;"	r	module:procedural
13encode	input.sv	/^    logic [2:0] encode ;$/;"	r	module:procedural
14s	input.sv	/^  string s;$/;"	r	module:procedural
15value	input.sv	/^  int value, a[3];$/;"	r	module:procedural
16a	input.sv	/^  int value, a[3];$/;"	r	module:procedural
17offset	input.sv	/^  int offset = 10;$/;"	r	module:procedural
18N	input.sv	/^  parameter N = 8;$/;"	c	module:procedural
19outer	input.sv	/^    for (int i = 0; i < N; i++) begin:outer$/;"	b	module:procedural
20inner	input.sv	/^      for (int j = 0; j < N; j++) begin : inner$/;"	b	block:procedural.outer
21state	input.sv	/^    enum { FSM_IDLE, FSM_ITER } state;$/;"	E	module:procedural
22FSM_IDLE	input.sv	/^    enum { FSM_IDLE, FSM_ITER } state;$/;"	c	enum:procedural.state
23FSM_ITER	input.sv	/^    enum { FSM_IDLE, FSM_ITER } state;$/;"	c	enum:procedural.state
24