1// 2// LRM: 26. Packages 3// 4// 26.2 Package declarations 5package ComplexPkg; 6 typedef struct { 7 shortreal i, r; 8 } Complex; 9 10 function Complex add(Complex a, b); 11 add.r = a.r + b.r; 12 add.i = a.i + b.i; 13 endfunction 14 15 function Complex mul(Complex a, b); 16 mul.r = (a.r * b.r) - (a.i * b.i); 17 mul.i = (a.r * b.i) + (a.i * b.r); 18 endfunction 19endpackage : ComplexPkg 20 21// 26.3 Referencing data in packages 22package p; 23 typedef enum { FALSE, TRUE } bool_t; 24endpackage 25 26package q; 27 typedef enum { ORIGINAL, FALSE } teeth_t; 28endpackage 29 30module top1 ; 31 import p::*; 32 import q::teeth_t; 33 34 teeth_t myteeth; 35 36 initial begin 37 myteeth = q:: FALSE; // OK: 38 //myteeth = FALSE; // ERROR: Direct reference to FALSE refers to the 39 end // FALSE enumeration literal imported from p 40endmodule 41 42module top2 ; 43 import p::*; 44 import q::teeth_t, q::ORIGINAL, q::FALSE; 45 46 teeth_t myteeth; 47 48 initial begin 49 myteeth = FALSE; // OK: Direct reference to FALSE refers to the 50 end // FALSE enumeration literal imported from q 51endmodule 52 53// 26.4 Using packages in module headers 54package A; 55 typedef struct { 56 bit [ 7:0] opcode; 57 bit [23:0] addr; 58 } instruction_t; 59endpackage: A 60 61package B; 62 typedef enum bit {FALSE, TRUE} boolean_t; 63endpackage: B 64 65module M import A::instruction_t, B::*; 66 #(WIDTH = 32) 67 (input [WIDTH-1:0] data, 68 input instruction_t a, 69 output [WIDTH-1:0] result, 70 output boolean_t OK 71 ); 72 // ... 73endmodule: M 74 75// original 76package MyPackage; 77 typedef struct { 78 shortreal a; 79 real b; 80 } MyData; 81 function MyData add(MyData x, y); 82 add.a = x.a + y.a; 83 endfunction 84 function MyData mul(MyData x, y); 85 mul.b = x.b * y.b; 86 endfunction 87endpackage : MyPackage 88 89reg var_to_check_context; 90 91// multiple package import declarations, #3150 92module mod_a 93 import A::*, B::*; 94( 95 input var logic in_a 96); 97 logic sig_a; 98endmodule 99 100module mod_b 101 import A::*; 102 import B::*; 103( 104 input var logic in_b 105); 106 logic sig_b; 107endmodule 108