xref: /Universal-ctags/Units/parser-verilog.r/systemverilog-package.d/expected.tags (revision 46313f460f7c57588df5217354db1556fe155f26)
1ComplexPkg	input.sv	/^package ComplexPkg;$/;"	K
2Complex	input.sv	/^    } Complex;$/;"	T	package:ComplexPkg
3i	input.sv	/^        shortreal i, r;$/;"	w	typedef:ComplexPkg.Complex
4r	input.sv	/^        shortreal i, r;$/;"	w	typedef:ComplexPkg.Complex
5add	input.sv	/^    function Complex add(Complex a, b);$/;"	f	package:ComplexPkg
6a	input.sv	/^    function Complex add(Complex a, b);$/;"	p	function:ComplexPkg.add
7b	input.sv	/^    function Complex add(Complex a, b);$/;"	p	function:ComplexPkg.add
8mul	input.sv	/^    function Complex mul(Complex a, b);$/;"	f	package:ComplexPkg
9a	input.sv	/^    function Complex mul(Complex a, b);$/;"	p	function:ComplexPkg.mul
10b	input.sv	/^    function Complex mul(Complex a, b);$/;"	p	function:ComplexPkg.mul
11p	input.sv	/^package p;$/;"	K
12bool_t	input.sv	/^    typedef enum { FALSE, TRUE } bool_t;$/;"	T	package:p
13FALSE	input.sv	/^    typedef enum { FALSE, TRUE } bool_t;$/;"	c	typedef:p.bool_t
14TRUE	input.sv	/^    typedef enum { FALSE, TRUE } bool_t;$/;"	c	typedef:p.bool_t
15q	input.sv	/^package q;$/;"	K
16teeth_t	input.sv	/^    typedef enum { ORIGINAL, FALSE } teeth_t;$/;"	T	package:q
17ORIGINAL	input.sv	/^    typedef enum { ORIGINAL, FALSE } teeth_t;$/;"	c	typedef:q.teeth_t
18FALSE	input.sv	/^    typedef enum { ORIGINAL, FALSE } teeth_t;$/;"	c	typedef:q.teeth_t
19top1	input.sv	/^module top1 ;$/;"	m
20myteeth	input.sv	/^    teeth_t myteeth;$/;"	r	module:top1
21top2	input.sv	/^module top2 ;$/;"	m
22myteeth	input.sv	/^    teeth_t myteeth;$/;"	r	module:top2
23A	input.sv	/^package A;$/;"	K
24instruction_t	input.sv	/^    } instruction_t;$/;"	T	package:A
25opcode	input.sv	/^        bit [ 7:0] opcode;$/;"	w	typedef:A.instruction_t
26addr	input.sv	/^        bit [23:0] addr;$/;"	w	typedef:A.instruction_t
27B	input.sv	/^package B;$/;"	K
28boolean_t	input.sv	/^    typedef enum bit {FALSE, TRUE} boolean_t;$/;"	T	package:B
29FALSE	input.sv	/^    typedef enum bit {FALSE, TRUE} boolean_t;$/;"	c	typedef:B.boolean_t
30TRUE	input.sv	/^    typedef enum bit {FALSE, TRUE} boolean_t;$/;"	c	typedef:B.boolean_t
31M	input.sv	/^module M import A::instruction_t, B::*;$/;"	m
32WIDTH	input.sv	/^    #(WIDTH = 32)$/;"	c	module:M
33data	input.sv	/^     (input [WIDTH-1:0] data,$/;"	p	module:M
34a	input.sv	/^      input instruction_t a,$/;"	p	module:M
35result	input.sv	/^      output [WIDTH-1:0] result,$/;"	p	module:M
36OK	input.sv	/^      output boolean_t OK$/;"	p	module:M
37MyPackage	input.sv	/^package MyPackage;$/;"	K
38MyData	input.sv	/^    } MyData;$/;"	T	package:MyPackage
39a	input.sv	/^        shortreal a;$/;"	w	typedef:MyPackage.MyData
40b	input.sv	/^        real b;$/;"	w	typedef:MyPackage.MyData
41add	input.sv	/^    function MyData add(MyData x, y);$/;"	f	package:MyPackage
42x	input.sv	/^    function MyData add(MyData x, y);$/;"	p	function:MyPackage.add
43y	input.sv	/^    function MyData add(MyData x, y);$/;"	p	function:MyPackage.add
44mul	input.sv	/^    function MyData mul(MyData x, y);$/;"	f	package:MyPackage
45x	input.sv	/^    function MyData mul(MyData x, y);$/;"	p	function:MyPackage.mul
46y	input.sv	/^    function MyData mul(MyData x, y);$/;"	p	function:MyPackage.mul
47var_to_check_context	input.sv	/^reg var_to_check_context;$/;"	r
48mod_a	input.sv	/^module mod_a$/;"	m
49in_a	input.sv	/^    input var logic in_a$/;"	p	module:mod_a
50sig_a	input.sv	/^    logic sig_a;$/;"	r	module:mod_a
51mod_b	input.sv	/^module mod_b$/;"	m
52in_b	input.sv	/^    input var logic in_b$/;"	p	module:mod_b
53sig_b	input.sv	/^    logic sig_b;$/;"	r	module:mod_b
54