1// LRM 6.3 Data types 2module net_decl; 3 // 6.3.2.1 Charge strength 4 trireg a; 5 trireg (large) #(0,0,50) cap1; 6 trireg (small) signed [3:0] cap2; 7 8 // 6.5 Nets and variables 9 wire w = vara & varb; // net with a continuous assignment 10 logic v = consta & constb; // variable with initialization 11 logic vw; // no initial assignment 12 assign vw = vara & varb; // continuous assignment to a variable 13 real circ; 14 assign circ = 2.0 * PI * R; // continuous assignment to a variable 15 16 // 6.6 Net types 17 // 6.6.7 User-defined nettypes 18 // add later !!! 19endmodule 20 21// 6.6.8 Generic interconnect 22module top(); 23 interconnect [0:1] iBus; 24 lDriver l1(iBus[0]); 25 rDriver r1(iBus[1]); 26 rlMod m1(iBus); 27endmodule : top 28 29module rlMod(input interconnect [0:1] iBus); 30 lMod l1(iBus[0]); 31 rMod r1(iBus[1]); 32endmodule : rlMod 33 34// 6.7 Net declarations 35module Net_declarations; 36 // 6.7.1 Net declarations with built-in net types 37 trireg (large) logic #(0,0,0) cap1; 38 typedef logic [31:0] addressT; 39 wire addressT w1; 40 wire struct packed { logic ecc; logic [7:0] data; } memsig; 41 42 wire w; // equivalent to "wire logic w;" 43 wire logic w; 44 wire [15:0] ww; // equivalent to "wire logic [15:0] ww;" 45 wire logic [15:0] ww; 46 47 interconnect w1; // legal 48 interconnect [3:0] w2; // legal 49 interconnect [3:0] w3 [1:0]; // legal 50 51 // 6.7.2 Net declarations with user-defined nettypes 52 nettype T wT; 53 nettype T wTsum with Tsum; 54 wT w1; 55 wT w2[8]; 56 wTsum w3; 57 wTsum w4[8]; 58 typedef real TR[5]; 59 nettype TR wTR; 60 wTR w5; 61 wTR w6[8]; 62endmodule 63 64// 6.8 Variable declarations 65module Variable_declarations; 66 shortint s1, s2[0:9]; 67 68 var v; // equivalent to "var logic v;" 69 var [15:0] vw; // equivalent to "var logic [15:0] vw;" 70 var enum bit { clear, error } status; 71 input var logic data_in; 72 var reg r; 73 74 int i = 0; 75endmodule 76 77// 6.9 Vector declarations 78module Vector_declarations; 79 // 6.9.1 Specifying vectors 80 wand w; // a scalar "wand" net 81 tri [15:0] busa; // a 16-bit bus 82 trireg (small) storeit; // a charge storage node of strength small 83 logic a; // a scalar variable 84 logic[3:0] v; // a 4-bit vector made up of (from most to 85 // least significant)v[3], v[2], v[1], and v[0] 86 logic signed [3:0] signed_reg; // a 4-bit vector in range -8 to 7 87 logic [-1:4] b; // a 6-bit vector 88 wire w1, w2; // declares two nets 89 logic [4:0] x, y, z; // declares three 5-bit variables 90 91 // 6.9.2 Vector net accessibility 92 tri1 scalared [63:0] bus64; //a bus that will be expanded 93 tri vectored [31:0] data; //a bus that may or may not be expanded 94endmodule 95 96// 6.16 String data type 97module String_data_type; 98 parameter string default_name = "John Smith"; 99 string myName = default_name; 100 101 byte c = "A"; // assigns to c "A" 102 bit [10:0] b = "\x41"; // assigns to b 'b000_0100_0001 103 bit [1:4][7:0] h = "hello" ; // assigns to h "ello" 104 105 string s0 = "String literal assign";// sets s0 to "String literal assign" 106 string s1 = "hello\0world"; // sets s1 to "helloworld" 107 bit [11:0] b = 12'ha41; 108 string s2 = string'(b); // sets s2 to 16'h0a41 109 110 typedef logic [15:0] r_t; 111 r_t r; 112 integer i = 1; 113 string b = ""; 114 string a = {"Hi", b}; 115 r = r_t'(a); // OK 116 b = string'(r); // OK 117 b = "Hi"; // OK 118 b = {5{"Hi"}}; // OK 119 a = {i{"Hi"}}; // OK (non-constant replication) 120 //r = {i{"Hi"}}; // invalid (non-constant replication) 121 a = {i{b}}; // OK 122 a = {a,b}; // OK 123 a = {"Hi",b}; // OK 124 r = {"H",""}; // yields "H\0". "" is converted to 8'b0 125 b = {"H",""}; // yields "H". "" is the empty string 126 a[0] = "h"; // OK, same as a[0] = "cough" 127 //a[0] = b; // invalid, requires a cast 128 a[1] = "\0"; // ignored, a is unchanged 129endmodule 130 131// 6.17 Event data type 132module event_data_type; 133 event done; // declare a new event called done 134 event done_too = done; // declare done_too as alias to done 135 event empty = null; // event variable with no synchronization object 136endmodule 137 138// 6.18 User-defined types 139module user_define_types_0; 140 typedef int intP; 141 intP a, b; 142endmodule 143 144interface intf_i; 145 typedef int data_t; 146endinterface 147 148// interface based typedef 149module sub(intf_i p); 150 typedef p.data_t my_data_t; 151 my_data_t data; 152endmodule 153 154// interface based typedef with constant bit select 155module cbs; 156 typedef p[10].data_t cbs_t; 157endmodule 158 159module user_define_types_1; 160 // forward typedef 161 typedef enum type_identifier; 162 typedef struct type_identifier; 163 typedef union type_identifier; 164 typedef class type_identifier; 165 typedef interface class type_identifier; 166 typedef type_identifier; 167endmodule 168 169// 6.19 Enumerations 170module enum_test; 171 enum {red, yellow, green} light1, light2; // anonymous int type 172 // Syntax error: IDLE=2'b00, XX=2'bx <ERROR>, S1=2'b01, S2=2'b10 173 //enum bit [1:0] {IDLE, XX='x, S1=2'b01, S2=2'b10} state, next; 174 // Correct: IDLE=0, XX='x, S1=1, S2=2 175 enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next; 176 // Syntax error: IDLE=0, XX='x, S1=??, S2=?? 177 //enum integer {IDLE, XX='x, S1, S2} state, next; 178 enum {bronze=3, silver, gold} medal; // silver=4, gold=5 179 180 // Correct declaration - bronze and gold are unsized 181 enum bit [3:0] {bronze='h3, silver, gold='h5} medal2; 182 // Correct declaration - bronze and gold sizes are redundant 183 enum bit [3:0] {bronze=4'h3, silver, gold=4'h5} medal3; 184 185 // 6.19.1 Defining new data types as enumerated types 186 typedef enum {NO, YES} boolean; 187 boolean myvar; // named type 188 189 // 6.19.2 Enumerated type ranges 190 typedef enum { add=10, sub[5], jmp[6:8] } E1; // FIXME 191 enum { register[2] = 1, register[2:4] = 10 } vr; // FIXME 192 193 // original 194 enum logic signed [3:0] { foo, bar } [1:0] cmplx_enum1; 195 enum logic unsigned [3:0] { foo, bar } [] cmplx_enum2; 196 197endmodule 198 199// 9.4.1 Delay control 200module delay_control #(d, e); 201 int rega, regb, regr; 202 initial begin 203 #10 rega = regb; 204 #d rega = regb; // d is defined as a parameter 205 #((d+e)/2) rega = regb; // delay is average of d and e 206 #regr regr = regr + 1; // delay is the value in regr 207 end 208endmodule 209 210// 10.3 Continuous assignments 211module delay_control_wire #(d, e); 212 wire wirea #10 = wireb; 213 wire wireb #d = wireb; 214 wire wirec #((d+e)/2) = wireb; 215 wire wired #wirer = wirer + 1; 216 wire w$ire, wire$; // '$' included 217endmodule 218 219// orignal : LRM 5.8 Time literals 220module rst; 221 logic trst_n; 222 initial begin 223 #10.5fs trst_n = 1'b0; 224 #10ps trst_n = 1'b1; 225 #10ns trst_n = 1'b0; 226 #10us trst_n = 1'b1; 227 #10ms trst_n = 1'b0; 228 #10s trst_n = 1'b1; 229 end 230endmodule 231