1// 2// Clocking blocks tests 3// 4 5// LRM 14.3 Clocking block declaration 6interface foo_bus; 7 logic clock1; 8 logic data, ready, enable, ack, addr; 9 10 clocking bus @(posedge clock1); 11 default input #10ns output #2ns; 12 input data, ready, enable = top.mem1.enable; 13 output negedge ack; 14 input #1step addr; 15 endclocking 16endinterface 17 18// 14.4 Input and output skews 19module foo_14_4; 20 logic clk, address, data; 21 clocking dram @(clk); 22 input #1ps address; 23 input #5 output #6 data; 24 endclocking 25endmodule 26 27// 14.8 Multiple clocking blocks example 28program test( input phi1, input [15:0] data, output logic write, 29 input phi2, inout [8:1] cmd, input enable 30); 31 reg [8:1] cmd_reg; 32 clocking cd1 @(posedge phi1); 33 input data; 34 output write; 35 input state = top.cpu1.state; 36 endclocking 37 38 clocking cd2 @(posedge phi2); 39 input #2 output #4ps cmd; 40 input enable; 41 endclocking 42 43 initial begin 44 // program begins here 45 // ... 46 // user can access cd1.data , cd2.cmd , etc… 47 end 48 49 assign cmd = enable ? cmd_reg: 'x; 50endprogram 51 52// 14.14 Global clocking 53module top; 54logic clk1, clk2; 55 global clocking sys @(clk1 or clk2); endclocking 56 // ... 57endmodule 58