xref: /Universal-ctags/Units/parser-verilog.r/systemverilog-block.d/input.sv (revision 4aaf731aca33339bab9e0f2fd14ed86eca1d85b6)
1//
2// block test
3//
4
5// LRM 9.3.2 Parallel blocks
6module test;
7  logic r;
8  initial begin
9    fork
10      #50 r = 'h35;
11      #100 r = 'hE2;
12      #150 r = 'h00;
13      #200 r = 'hF7;
14    join
15  end
16
17  event enable_a, enable_b;
18  logic wa, wb;
19  time  ta, tb;
20  initial
21    fork: fork_1
22      @enable_a
23      begin
24        #ta wa = 0;
25        #ta wa = 1;
26        #ta wa = 0;
27      end
28      @enable_b
29      begin
30        #tb wb = 1;
31        #tb wb = 0;
32        #tb wb = 1;
33      end
34    join
35endmodule
36
37// LRM 9.3.4 Block names
38
39// orignal tests
40module block1 #(N_IF = 8) (
41  input logic clk, rst_n
42);
43  generate for (genvar gi = 0; gi < N_IF; ++gi) begin : b_g1
44
45    always_ff @(posedge clk, negedge rst_n) begin
46      logic a;
47      if (~rst_n) begin
48        ;
49      end
50    end
51    logic var_b_g;
52
53  end endgenerate
54
55  for (genvar gi = 0; gi < N_IF; ++gi) begin : b_g2
56
57    always_comb begin:b1
58        logic lb1;
59        begin :b2_1
60          logic lb2;
61        end:b2_1
62        begin :b2_2
63          logic lb2;
64        end:b2_2
65    end : b1
66    logic var_b_g;
67
68  end : b_g2
69
70endmodule : block1
71
72// fixed by sv-kind-fixes
73class nested_block;
74  function void func (input logic a, b);
75    if (a) begin : outer_block
76      if (b) begin : inner_block
77        ;
78      end : inner_block
79    end // no block label
80  endfunction
81
82  logic p; // class:nested_block
83endclass : nested_block
84