xref: /Universal-ctags/Units/parser-verilog.r/systemverilog-assignment.d/expected.tags (revision 31730736bc3e251d2b19154196de4fe409cd7cdc)
1assignment	input.sv	/^module assignment;$/;"	m
2bar	input.sv	/^  function int bar();$/;"	f	module:assignment
3msg	input.sv	/^  string msg = $sformatf("GP miscompare between '%s' and '%s':\\nlhs = %s\\nrhs = %s",$/;"	r	module:assignment
4unpackedbits	input.sv	/^  bit unpackedbits [1:0] = '{1,1};$/;"	r	module:assignment
5unpackedints	input.sv	/^  int unpackedints [1:0] = '{1'b1, 1'b1};$/;"	r	module:assignment
6y	input.sv	/^  int y;$/;"	r	module:assignment
7unpackedints2	input.sv	/^  int unpackedints2 [1:0] = '{2 {y}};$/;"	r	module:assignment
8n	input.sv	/^  int n[1:2][1:3] = '{2{'{3{y}}}};$/;"	r	module:assignment
9abkey	input.sv	/^  struct {int a; time b;} abkey[1:0];$/;"	S	module:assignment
10a	input.sv	/^  struct {int a; time b;} abkey[1:0];$/;"	w	struct:assignment.abkey
11b	input.sv	/^  struct {int a; time b;} abkey[1:0];$/;"	w	struct:assignment.abkey
12abkey_fun	input.sv	/^  struct {int a; time b;} abkey_fun[1:0] = '{'{a:bar(), b:2ns}, '{int:5, time:$time}};$/;"	S	module:assignment
13a	input.sv	/^  struct {int a; time b;} abkey_fun[1:0] = '{'{a:bar(), b:2ns}, '{int:5, time:$time}};$/;"	w	struct:assignment.abkey_fun
14b	input.sv	/^  struct {int a; time b;} abkey_fun[1:0] = '{'{a:bar(), b:2ns}, '{int:5, time:$time}};$/;"	w	struct:assignment.abkey_fun
15st	input.sv	/^  } st;$/;"	T	module:assignment
16x	input.sv	/^    int x;$/;"	w	typedef:assignment.st
17y	input.sv	/^    int y;$/;"	w	typedef:assignment.st
18k	input.sv	/^  int k = 1;$/;"	r	module:assignment
19s1	input.sv	/^  st s1 = '{1, 2+k}; \/\/ by position;$/;"	r	module:assignment
20s2	input.sv	/^  st s2 = '{x:2, y:3+k}; \/\/ by name$/;"	r	module:assignment
21s3	input.sv	/^  struct { int x; int y; } s3 = '{1, 2+k};$/;"	S	module:assignment
22x	input.sv	/^  struct { int x; int y; } s3 = '{1, 2+k};$/;"	w	struct:assignment.s3
23y	input.sv	/^  struct { int x; int y; } s3 = '{1, 2+k};$/;"	w	struct:assignment.s3
24s4	input.sv	/^  struct { int x; int y; } s4 = '{x:2, y:3+k};$/;"	S	module:assignment
25x	input.sv	/^  struct { int x; int y; } s4 = '{x:2, y:3+k};$/;"	w	struct:assignment.s4
26y	input.sv	/^  struct { int x; int y; } s4 = '{x:2, y:3+k};$/;"	w	struct:assignment.s4
27s5	input.sv	/^  st s5 = '{default:2};$/;"	r	module:assignment
28ab	input.sv	/^  typedef struct { int a; shortreal b; } ab;  \/\/ LRM 5.10$/;"	T	module:assignment
29a	input.sv	/^  typedef struct { int a; shortreal b; } ab;  \/\/ LRM 5.10$/;"	w	typedef:assignment.ab
30b	input.sv	/^  typedef struct { int a; shortreal b; } ab;  \/\/ LRM 5.10$/;"	w	typedef:assignment.ab
31abkey	input.sv	/^  ab abkey[1:0] = '{'{a:1, b:1.0}, '{int:2, shortreal:2.0}};$/;"	r	module:assignment
32ABC	input.sv	/^  } ABC, DEF;$/;"	S	module:assignment
33A	input.sv	/^    int A;$/;"	w	struct:assignment.ABC
34BC1	input.sv	/^    } BC1, BC2;$/;"	w	struct:assignment.ABC
35BC2	input.sv	/^    } BC1, BC2;$/;"	w	struct:assignment.ABC
36DEF	input.sv	/^  } ABC, DEF;$/;"	S	module:assignment
37A	input.sv	/^    int A;$/;"	w	struct:assignment.DEF
38BC1	input.sv	/^    } BC1, BC2;$/;"	w	struct:assignment.DEF
39BC2	input.sv	/^    } BC1, BC2;$/;"	w	struct:assignment.DEF
40sa	input.sv	/^  } sa;$/;"	T	module:assignment
41a	input.sv	/^    logic [7:0] a;$/;"	w	typedef:assignment.sa
42b	input.sv	/^    bit b;$/;"	w	typedef:assignment.sa
43c	input.sv	/^    bit signed [31:0] c;$/;"	w	typedef:assignment.sa
44s	input.sv	/^    string s;$/;"	w	typedef:assignment.sa
45s2	input.sv	/^  sa s2 = '{int:1, default:0, string:""};$/;"	r	module:assignment
46A3	input.sv	/^  int A3[1:3];$/;"	r	module:assignment
47AI3	input.sv	/^  typedef int AI3[1:3];$/;"	T	module:assignment
48A3	input.sv	/^  AI3 A3;$/;"	r	module:assignment
49A9	input.sv	/^  int A9[1:9];$/;"	r	module:assignment
50