1deferred_immediate_assertions input.sv /^initial begin : deferred_immediate_assertions$/;" b 2immediate_assertion input.sv /^ immediate_assertion : assert () myTask();$/;" A block:deferred_immediate_assertions 3immediate_cover input.sv /^ immediate_cover : cover () myTask();$/;" A block:deferred_immediate_assertions 4immediate_assume input.sv /^ immediate_assume : assume () myTask();$/;" A block:deferred_immediate_assertions 5deferred_assertion1 input.sv /^ deferred_assertion1 : assert #0 () myTask();$/;" A block:deferred_immediate_assertions 6deferred_cover1 input.sv /^ deferred_cover1 : cover #0 () myTask();$/;" A block:deferred_immediate_assertions 7deferred_assume1 input.sv /^ deferred_assume1 : assume #0 () myTask();$/;" A block:deferred_immediate_assertions 8deferred_assertion2 input.sv /^ deferred_assertion2 : assert final () myTask();$/;" A block:deferred_immediate_assertions 9deferred_cover2 input.sv /^ deferred_cover2 : cover final () myTask();$/;" A block:deferred_immediate_assertions 10deferred_assume2 input.sv /^ deferred_assume2 : assume final () myTask();$/;" A block:deferred_immediate_assertions 11prop1 input.sv /^property prop1 ($/;" R 12m input.sv /^ local input int m,$/;" p property:prop1 13n input.sv /^ logic [1:0] n,$/;" p property:prop1 14o input.sv /^ int o$/;" p property:prop1 15prop2 input.sv /^property prop2 (a, b);$/;" R 16a input.sv /^property prop2 (a, b);$/;" p property:prop2 17b input.sv /^property prop2 (a, b);$/;" p property:prop2 18concurrent_assertion1 input.sv /^concurrent_assertion1 : assert property prop2 (l, m);$/;" A 19assert_test input.sv /^module assert_test;$/;" m 20assert_f input.sv /^ assert_f: assert(f) $info("passed"); else $error("failed");$/;" A module:assert_test 21assume_inputs input.sv /^ assume_inputs: assume (in_a || in_b) $info("assumption holds");$/;" A module:assert_test 22cover_a_and_b input.sv /^ cover_a_and_b: cover (in_a && in_b) $info("in_a && in_b == 1 covered");$/;" A module:assert_test 23t input.sv /^ time t;$/;" r module:assert_test 24b1 input.sv /^ always_comb begin : b1$/;" b module:assert_test 25a1 input.sv /^ a1: assert (not_a != a);$/;" A block:assert_test.b1 26a2 input.sv /^ a2: assert #0 (not_a != a); \/\/ Should pass once values have settled$/;" A block:assert_test.b1 27b1 input.sv /^ always_comb begin : b1$/;" b module:assert_test 28c1 input.sv /^ c1: cover (b != a);$/;" A block:assert_test.b1 29c2 input.sv /^ c2: cover #0 (b != a);$/;" A block:assert_test.b1 30error_type input.sv /^ function int error_type (int opcode);$/;" f module:assert_test 31opcode input.sv /^ function int error_type (int opcode);$/;" p function:assert_test.error_type 32func_assert input.sv /^ func_assert: assert (opcode < 64) else $display("Opcode error.");$/;" A function:assert_test.error_type 33b1 input.sv /^ always_comb begin : b1$/;" b module:assert_test 34a1 input.sv /^ a1: assert #0 (my_cond) else$/;" A block:assert_test.b1 35a2 input.sv /^ a2: assert #0 (my_cond) else$/;" A block:assert_test.b1 36dut input.sv /^module dut(input logic clk, input logic a, input logic b);$/;" m 37clk input.sv /^module dut(input logic clk, input logic a, input logic b);$/;" p module:dut 38a input.sv /^module dut(input logic clk, input logic a, input logic b);$/;" p module:dut 39b input.sv /^module dut(input logic clk, input logic a, input logic b);$/;" p module:dut 40c input.sv /^ logic c;$/;" r module:dut 41a1 input.sv /^ a1: assert #0 (!(a & c)) $display("Pass"); else $display("Fail");$/;" A module:dut 42a2 input.sv /^ a2: assert final (!(a & c)) $display("Pass"); else $display("Fail");$/;" A module:dut 43tb input.sv /^program tb(input logic clk, output logic a, output logic b);$/;" P 44clk input.sv /^program tb(input logic clk, output logic a, output logic b);$/;" p program:tb 45a input.sv /^program tb(input logic clk, output logic a, output logic b);$/;" p program:tb 46b input.sv /^program tb(input logic clk, output logic a, output logic b);$/;" p program:tb 47m input.sv /^ default clocking m @(posedge clk);$/;" L program:tb 48sva_svtb input.sv /^module sva_svtb;$/;" m 49clk input.sv /^ bit clk;$/;" r module:sva_svtb 50a input.sv /^ logic a, b;$/;" r module:sva_svtb 51b input.sv /^ logic a, b;$/;" r module:sva_svtb 52dut input.sv /^ dut dut (.*);$/;" i module:sva_svtb 53tb input.sv /^ tb tb (.*);$/;" i module:sva_svtb 54m input.sv /^module m (input a, b);$/;" m 55a input.sv /^module m (input a, b);$/;" p module:m 56b input.sv /^module m (input a, b);$/;" p module:m 57a1 input.sv /^ a1: assert #0 (a == b);$/;" A module:m 58m input.sv /^module m (input a, b);$/;" m 59a input.sv /^module m (input a, b);$/;" p module:m 60b input.sv /^module m (input a, b);$/;" p module:m 61a1 input.sv /^ a1: assert #0 (a == b);$/;" A module:m 62m input.sv /^module m (input bad_val, bad_val_ok, a, b, c, clear_b2);$/;" m 63bad_val input.sv /^module m (input bad_val, bad_val_ok, a, b, c, clear_b2);$/;" p module:m 64bad_val_ok input.sv /^module m (input bad_val, bad_val_ok, a, b, c, clear_b2);$/;" p module:m 65a input.sv /^module m (input bad_val, bad_val_ok, a, b, c, clear_b2);$/;" p module:m 66b input.sv /^module m (input bad_val, bad_val_ok, a, b, c, clear_b2);$/;" p module:m 67c input.sv /^module m (input bad_val, bad_val_ok, a, b, c, clear_b2);$/;" p module:m 68clear_b2 input.sv /^module m (input bad_val, bad_val_ok, a, b, c, clear_b2);$/;" p module:m 69b1 input.sv /^ always @(bad_val or bad_val_ok) begin : b1$/;" b module:m 70a1 input.sv /^ a1: assert #0 (bad_val) else $fatal(1, "Sorry");$/;" A block:m.b1 71b2 input.sv /^ always @(a or b or c) begin : b2$/;" b module:m 72a2 input.sv /^ a2: assert #0 (a && b);$/;" A block:m.b2 73a3 input.sv /^ a3: assert #0 (a || b);$/;" A block:m.b2 74b3 input.sv /^ always @(clear_b2) begin : b3$/;" b module:m 75m input.sv /^module m;$/;" m 76a input.sv /^ bit a;$/;" r module:m 77b input.sv /^ integer b;$/;" r module:m 78q input.sv /^ byte q[$];$/;" r module:m 79p1 input.sv /^ property p1;$/;" R module:m 80p2 input.sv /^ property p2;$/;" R module:m 81l_b input.sv /^ integer l_b;$/;" r property:m.p2 82count input.sv /^ bit [2:0] count;$/;" r module:m 83t input.sv /^ realtime t;$/;" r module:m 84p1 input.sv /^ property p1;$/;" R module:m 85p2 input.sv /^ property p2;$/;" R module:m 86l_t input.sv /^ realtime l_t;$/;" r property:m.p2 87m input.sv /^module m;$/;" m 88delay_example input.sv /^ sequence delay_example(x, y, min, max, delay1);$/;" q module:m 89x input.sv /^ sequence delay_example(x, y, min, max, delay1);$/;" p sequence:m.delay_example 90y input.sv /^ sequence delay_example(x, y, min, max, delay1);$/;" p sequence:m.delay_example 91min input.sv /^ sequence delay_example(x, y, min, max, delay1);$/;" p sequence:m.delay_example 92max input.sv /^ sequence delay_example(x, y, min, max, delay1);$/;" p sequence:m.delay_example 93delay1 input.sv /^ sequence delay_example(x, y, min, max, delay1);$/;" p sequence:m.delay_example 94a1 input.sv /^ a1: assert property (@(posedge clk) delay_example(x, y, 3, $, 2));$/;" A module:m 95z input.sv /^ int z, d;$/;" r module:m 96d input.sv /^ int z, d;$/;" r module:m 97s1 input.sv /^ sequence s1;$/;" q module:m 98s2 input.sv /^ sequence s2;$/;" q module:m 99s3 input.sv /^ sequence s3;$/;" q module:m 100s4 input.sv /^ sequence s4;$/;" q module:m 101s20_1 input.sv /^ sequence s20_1(data,en);$/;" q module:m 102data input.sv /^ sequence s20_1(data,en);$/;" p sequence:m.s20_1 103en input.sv /^ sequence s20_1(data,en);$/;" p sequence:m.s20_1 104s input.sv /^ sequence s;$/;" q module:m 105rule input.sv /^ sequence rule;$/;" q module:m 106rule input.sv /^ sequence rule;$/;" q module:m 107m input.sv /^module m;$/;" m 108s1 input.sv /^ sequence s1(w, x, y);$/;" q module:m 109w input.sv /^ sequence s1(w, x, y);$/;" p sequence:m.s1 110x input.sv /^ sequence s1(w, x, y);$/;" p sequence:m.s1 111y input.sv /^ sequence s1(w, x, y);$/;" p sequence:m.s1 112s2 input.sv /^ sequence s2(w, y, bit x);$/;" q module:m 113w input.sv /^ sequence s2(w, y, bit x);$/;" p sequence:m.s2 114y input.sv /^ sequence s2(w, y, bit x);$/;" p sequence:m.s2 115x input.sv /^ sequence s2(w, y, bit x);$/;" p sequence:m.s2 116delay_arg_example input.sv /^ sequence delay_arg_example (max, shortint delay1, delay2, min);$/;" q module:m 117max input.sv /^ sequence delay_arg_example (max, shortint delay1, delay2, min);$/;" p sequence:m.delay_arg_example 118delay1 input.sv /^ sequence delay_arg_example (max, shortint delay1, delay2, min);$/;" p sequence:m.delay_arg_example 119delay2 input.sv /^ sequence delay_arg_example (max, shortint delay1, delay2, min);$/;" p sequence:m.delay_arg_example 120min input.sv /^ sequence delay_arg_example (max, shortint delay1, delay2, min);$/;" p sequence:m.delay_arg_example 121my_delay input.sv /^ parameter my_delay=2;$/;" c module:m 122event_arg_example input.sv /^ sequence event_arg_example (event ev);$/;" q module:m 123ev input.sv /^ sequence event_arg_example (event ev);$/;" p sequence:m.event_arg_example 124event_arg_example2 input.sv /^ sequence event_arg_example2 (reg sig);$/;" q module:m 125sig input.sv /^ sequence event_arg_example2 (reg sig);$/;" p sequence:m.event_arg_example2 126s input.sv /^ sequence s(bit a, bit b);$/;" q module:m 127a input.sv /^ sequence s(bit a, bit b);$/;" p sequence:m.s 128b input.sv /^ sequence s(bit a, bit b);$/;" p sequence:m.s 129loc_a input.sv /^ bit loc_a;$/;" r sequence:m.s 130m input.sv /^module m;$/;" m 131s input.sv /^ sequence s;$/;" q module:m 132u input.sv /^ logic u, v = a, w = v || b;$/;" r sequence:m.s 133v input.sv /^ logic u, v = a, w = v || b;$/;" r sequence:m.s 134w input.sv /^ logic u, v = a, w = v || b;$/;" r sequence:m.s 135e input.sv /^ property e;$/;" R module:m 136x input.sv /^ int x;$/;" r property:m.e 137m input.sv /^module m;$/;" m 138p3 input.sv /^ property p3;$/;" R module:m 139c1 input.sv /^ c1: cover property (@(posedge clk) a #-# p3);$/;" A module:m 140a1 input.sv /^ a1: assert property (@(posedge clk) a |-> p3);$/;" A module:m 141m input.sv /^module m;$/;" m 142p input.sv /^ property p;$/;" R module:m 143v input.sv /^ logic v = e;$/;" r property:m.p 144a1 input.sv /^ a1: assert property (@(posedge clk) f |=> p);$/;" A module:m 145p input.sv /^ property p;$/;" R module:m 146v input.sv /^ logic v;$/;" r property:m.p 147m input.sv /^module m;$/;" m 148abc input.sv /^ property abc(a, b, c);$/;" R module:m 149a input.sv /^ property abc(a, b, c);$/;" p property:m.abc 150b input.sv /^ property abc(a, b, c);$/;" p property:m.abc 151c input.sv /^ property abc(a, b, c);$/;" p property:m.abc 152env_prop input.sv /^ env_prop: assert property (abc(rst, in1, in2))$/;" A module:m 153abc input.sv /^ property abc(a, b, c);$/;" R module:m 154a input.sv /^ property abc(a, b, c);$/;" p property:m.abc 155b input.sv /^ property abc(a, b, c);$/;" p property:m.abc 156c input.sv /^ property abc(a, b, c);$/;" p property:m.abc 157env_prop input.sv /^ assume property (abc(req, gnt, rst)) else $error(”Assumption failed.”);$/;" A module:m 158a1 input.sv /^ a1:assume property ( @(posedge clk) req dist {0:=40, 1:=60} ) ;$/;" A module:m 159proto input.sv /^ property proto ;$/;" R module:m 160a1_assertion input.sv /^ a1_assertion:assert property ( @(posedge clk) req inside {0, 1} ) ;$/;" A module:m 161proto_assertion input.sv /^ property proto_assertion ;$/;" R module:m 162tst input.sv /^program tst;$/;" P 163data input.sv /^ integer data;$/;" r program:tst 164wait_for input.sv /^ task automatic wait_for( integer value, output bit success );$/;" t program:tst 165value input.sv /^ task automatic wait_for( integer value, output bit success );$/;" p task:tst.wait_for 166success input.sv /^ task automatic wait_for( integer value, output bit success );$/;" p task:tst.wait_for 167ok input.sv /^ bit ok;$/;" r program:tst 168A input.sv /^module A;$/;" m 169a input.sv /^ logic a, clk;$/;" r module:A 170clk input.sv /^ logic a, clk;$/;" r module:A 171cb_with_input input.sv /^ clocking cb_with_input @(posedge clk);$/;" L module:A 172p1 input.sv /^ property p1;$/;" R clocking:A.cb_with_input 173cb_without_input input.sv /^ clocking cb_without_input @(posedge clk);$/;" L module:A 174p1 input.sv /^ property p1;$/;" R clocking:A.cb_without_input 175p1 input.sv /^ property p1;$/;" R module:A 176p2 input.sv /^ property p2;$/;" R module:A 177a1 input.sv /^ a1: assert property (p1);$/;" A module:A 178a2 input.sv /^ a2: assert property (cb_with_input.p1);$/;" A module:A 179a3 input.sv /^ a3: assert property (p2);$/;" A module:A 180a4 input.sv /^ a4: assert property (cb_without_input.p1);$/;" A module:A 181C input.sv /^class C;$/;" C 182check_transfer_size input.sv /^ protected function void check_transfer_size();$/;" f class:C 183assert_transfer_size input.sv /^ assert_transfer_size : assert(trans_collected.size == 1) else begin$/;" A function:C.check_transfer_size 184check_transfer_data_size input.sv /^ protected function void check_transfer_data_size();$/;" f class:C 185