1// Taken from: 2// http://www.asic-world.com/vera/hdl1.html#Interface_Declaration 3interface sample_if { 4 // Other signals are sampled with respect to this 5 input clock CLOCK; 6 output reset PHOLD#1; 7 output enable PHOLD#1; 8 input [7:0] cout PSAMPLE #-1; 9 inout data PSAMPLE PHOLD NSAMPLE#-1 NHOLD #1; 10 input ddr_data_in PSAMPLE NSAMPLE; 11 input data_in PSAMPLE #-1 hdl_node "sample_if_verilog.data"; 12 input [7:0] count PSAMPLE #-1 hdl_node "sample_if_verilog.counter"; 13 output nenable PHOLD #1 hdl_node "sample_if_verilog.counter_en"; 14} 15