1/* 2 * MIT License 3 * 4 * Copyright (c) 2018 SCARV Project - <info@scarv.org> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in all 14 * copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25// 26// SCARV Project 27// 28// University of Bristol 29// 30// RISC-V Cryptographic Instruction Set Extension 31// 32// Reference Implementation 33// 34// 35 36localparam \SCARV_COP_INSN_SUCCESS = 3'b000; 37localparam SCARV_COP_INSN_ABORT = 3'b001; 38localparam SCARV_COP_INSN_BAD_INS = 3'b010; 39localparam SCARV_COP_INSN_BAD_LAD = 3'b100; 40localparam SCARV_COP_INSN_BAD_SAD = 3'b101; 41localparam SCARV_COP_INSN_LD_ERR = 3'b110; 42localparam SCARV_COP_INSN_ST_ERR = 3'b111; 43localparam \module = 3'b111; 44 45localparam SCARV_COP_ICLASS_PACKED_ARITH = 4'b0001; 46localparam SCARV_COP_ICLASS_TWIDDLE = 4'b0010; 47localparam SCARV_COP_ICLASS_LOADSTORE = 4'b0011; 48localparam SCARV_COP_ICLASS_RANDOM = 4'b0100; 49localparam SCARV_COP_ICLASS_MOVE = 4'b0101; 50localparam SCARV_COP_ICLASS_MP = 4'b0110; 51localparam SCARV_COP_ICLASS_BITWISE = 4'b0111; 52localparam SCARV_COP_ICLASS_AES = 4'b1000; 53localparam SCARV_COP_ICLASS_SHA3 = 4'b1001; 54 55localparam SCARV_COP_SCLASS_SHA3_XY = 5'b11000; 56localparam SCARV_COP_SCLASS_SHA3_X1 = 5'b11001; 57localparam SCARV_COP_SCLASS_SHA3_X2 = 5'b11010; 58localparam SCARV_COP_SCLASS_SHA3_X4 = 5'b11100; 59localparam SCARV_COP_SCLASS_SHA3_YX = 5'b11011; 60 61localparam SCARV_COP_SCLASS_SCATTER_B = 5'd0 ; 62localparam SCARV_COP_SCLASS_GATHER_B = 5'd1 ; 63localparam SCARV_COP_SCLASS_SCATTER_H = 5'd2 ; 64localparam SCARV_COP_SCLASS_GATHER_H = 5'd3 ; 65localparam SCARV_COP_SCLASS_ST_W = 5'd4 ; 66localparam SCARV_COP_SCLASS_LD_W = 5'd5 ; 67localparam SCARV_COP_SCLASS_ST_H = 5'd6 ; 68localparam SCARV_COP_SCLASS_LH_CR = 5'd7 ; 69localparam SCARV_COP_SCLASS_ST_B = 5'd8 ; 70localparam SCARV_COP_SCLASS_LB_CR = 5'd9 ; 71 72`ifdef FORMAL 73`include "fml_common.vh" 74`endif 75 76// 77// module: scarv_cop_cprs 78// 79// The general purpose register file used by the COP. 80// 81module scarv_cop_cprs ( 82 83input wire g_clk , // Global clock 84output wire g_clk_req , // Clock request 85input wire g_resetn , // Synchronous active low reset. 86 87`ifdef FORMAL 88`VTX_REGISTER_PORTS_OUT(cprs_snoop) 89`endif 90 91input wire crs1_ren , // Port 1 read enable 92input wire [ 3:0] crs1_addr , // Port 1 address 93output wire [31:0] crs1_rdata , // Port 1 read data 94 95input wire crs2_ren , // Port 2 read enable 96input wire [ 3:0] crs2_addr , // Port 2 address 97output wire [31:0] crs2_rdata , // Port 2 read data 98 99input wire crs3_ren , // Port 3 read enable 100input wire [ 3:0] crs3_addr , // Port 3 address 101output wire [31:0] crs3_rdata , // Port 3 read data 102 103input wire [ 3:0] crd_wen , // Port 4 write enable 104input wire [ 3:0] crd_addr , // Port 4 address 105input wire [31:0] crd_wdata // Port 4 write data 106 107); 108 109// Only need a clock when doing a write. 110assign g_clk_req = crd_wen; 111 112// Storage for the registers 113reg [31:0] cprs [15:0]; 114 115`ifdef FORMAL 116`VTX_REGISTER_PORTS_ASSIGNR(cprs_snoop,cprs) 117`endif 118 119// 120// Read port logic 121// 122 123assign crs1_rdata = {32{crs1_ren}} & cprs[crs1_addr]; 124assign crs2_rdata = {32{crs2_ren}} & cprs[crs2_addr]; 125assign crs3_rdata = {32{crs3_ren}} & cprs[crs3_addr]; 126 127// 128// Generate logic for each register. 129// 130genvar i; 131generate for (i = 0; i < 16; i = i + 1) begin : gen_cprs 132 133 always @(posedge g_clk) begin 134 135 if(!g_resetn) begin 136 `ifdef FORMAL 137 // If running the yosys formal flow, allow initial 138 // register values to be any constant value. 139 #1 cprs[i] <= $anyconst; 140 `else 141 #1step cprs[i] <= 32'b0; 142 `endif 143 144 end else if((|crd_wen) && (crd_addr == i)) begin 145 if(crd_wen[3]) cprs[i][31:24] <= crd_wdata[31:24]; 146 if(crd_wen[2]) cprs[i][23:16] <= crd_wdata[23:16]; 147 if(crd_wen[1]) cprs[i][15: 8] <= crd_wdata[15: 8]; 148 if(crd_wen[0]) cprs[i][ 7: 0] <= crd_wdata[ 7: 0]; 149 end 150 151 end 152 153end endgenerate 154 155endmodule 156